Host computers are typically interfaced to communication networks through an intelligent controller The controller offloads from the host much of the work associated with network communication so that the host is freed for other work. At any given time, the host may have in process several tasks requiring network communication, and the controller has corresponding tasks. Blocks of data must be transferred between tasks in the host and tasks in the controller in either direction. When data for a specified task is received on the network, the task in the controller must forward the data to the corresponding task in the host. Similarly, when a particular task in the host has data ready for transmission on the network, it is forwarded to the corresponding task in the controller. It is necessary that the transfer of data between multiple tasks in the host and multiple tasks in the controller be performed in an efficient, high-speed and noninterfering manner. Furthermore, the transfer should be performed with a minimum of host involvement.
It is desirable to utilize direct memory access (DMA) transfers of data between the host and the controller in order to achieve high speed. One limiting factor in performing DMA transfers is that the host typically has a larger address space than the controller. The controller may have a 16-bit address, while the host may have an address of 28 bits or more. Therefore, the controller can access only a segment, usually called an I/O segment, of the host virtual memory space. In order to transfer data from the controller to a specified page in the host memory or to transfer data from a specified page in the host memory to the controller, it is necessary for the host to map the specified page to virtual memory location that is accessible to the controller This mapping process, known as "windowing," is typically performed under host control. Consequently, in prior systems the data transfer took place at the time specified by the host, and in the order specified by the host.
It is a general object of the present invention to provide improved methods of communication between a host computer and an intelligent controller.
It is another object of the present invention to provide methods of efficient, noninterfering communication between multiple tasks on a host computer and multiple tasks on an intelligent controller.
It is a further object of the present invention to provide methods for communication between multiple tasks on a host computer and multiple tasks on a controller wherein the time and order of data transfer are determined by the controller.
It is yet another object of the present invention to provide methods for communication between multiple tasks on a host computer and multiple tasks on a controller utilizing direct memory access transfers.
It is a further object of the present invention to provide methods for communication between multiple tasks on a host computer and multiple tasks on a controller with a minimum of host computer involvement.